CXL: Separating Fact From Fiction
Emu (Nurin) | Tue 16 Apr 11:40 a.m.–12:25 p.m.
Presented by
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Peter Waskiewicz Jr (PJ) is a Senior Software Engineer in Jump Trading’s Linux engineering division, focusing on Linux kernel and device driver development and embedded systems.
Prior to Jump Trading, PJ spent the majority of his career at Intel, where he was responsible for writing and maintaining several of the Intel Ethernet Linux device drivers, and developing Linux kernel changes for scaling to 10GbE and beyond. PJ was also a Senior Principal Engineer at NetApp in the SolidFire division, where he was the chief Linux kernel and networking architect for the SolidFire scale-out cloud storage platform. He is also an adjunct faculty at Portland State University, teaching OS and Device Drivers in the Electrical and Computer Engineering Department.
Abstract
Compute eXpress Link, or CXL, is a new industry-standard interconnect looking to move bus connectivity beyond PCI Express. It promises to reduce latency, increase bandwidth, and add functionality for endpoint devices to have better connectivity with a host CPU. There are multiple revisions of the specifications available since the CXL Consortium publicly revealed CXL in 2019. But how does this nirvana of bus interconnect functionality match up with reality, and what is actually available to use this new technology?
This talk will first discuss what exactly is CXL, and why it actually is an exciting technology. Diving into the specifics of each sub-protocol, CXL.io, CXL.mem, and CXL.cache, each protocol will be covered why it truly is a great step beyond what PCIe is capable of doing today. It will then move onto the state of reality; where do the specifications line up with CPU support, where does the Linux kernel support land, and what devices actually exist.
Finally, this talk will cover what the near-future roadmap looks like, and how the reality of the CXL ecosystem will start to converge with the empty space of specifications.
Compute eXpress Link, or CXL, is a new industry-standard interconnect looking to move bus connectivity beyond PCI Express. It promises to reduce latency, increase bandwidth, and add functionality for endpoint devices to have better connectivity with a host CPU. There are multiple revisions of the specifications available since the CXL Consortium publicly revealed CXL in 2019. But how does this nirvana of bus interconnect functionality match up with reality, and what is actually available to use this new technology? This talk will first discuss what exactly is CXL, and why it actually is an exciting technology. Diving into the specifics of each sub-protocol, CXL.io, CXL.mem, and CXL.cache, each protocol will be covered why it truly is a great step beyond what PCIe is capable of doing today. It will then move onto the state of reality; where do the specifications line up with CPU support, where does the Linux kernel support land, and what devices actually exist. Finally, this talk will cover what the near-future roadmap looks like, and how the reality of the CXL ecosystem will start to converge with the empty space of specifications.